Registers in CPU – That diagram seems to describe a specific processor, and the specific names for some of its registers.
Different processors have different numbers and types of registers.
Most people focus architectural registers, and within the architectural registers, most folks especially focus on general purpose registers.
You might now be asking “what’s an architectural register?
An architectural register is a register implied by the instruction set architecture of the processor you’re using.
It’s architectural, in the sense that the architecture definition says that the register must exist, or at the very least, an implementation must give the illusion that the registers in CPU exists.
Architectural registers are the registers the programmer needs to be aware of when programming in assembly language.
When an assembly programmer thinks of a specific register by name, most often they’re thinking of an architectural register.
General Purpose Register
You might also wonder what I mean by “general purpose register,” versus other kinds.
A general purpose register can be used for arbitrary arithmetic.
Most instructions are able to use the general purpose registers for most purposes.
This is in contrast to special purpose registers, such as the program counter, which can really only be used for their dedicated purpose.
Micro architectural Registers
A given implementation will have some number of micro architectural registers.
These registers are specific to the implementation. These include pipeline registers, instruction decode registers, and so on.
The MBR, MAR, IR and IBR in your example above sound like microarchitectural registers. These generally are not directly accessible from assembly code.
Two different implementations of the same instruction set could have noticeably different sets of microarchitectural registers.
For example, the 8086 instruction set architecture defines a handful of general purpose registers, including AX, BX, CX, DX, SI, and DI.
It also defines some special purpose registers, such as the segment registers (CS, DS, ES, SS), instruction pointer (IP), the stack and base pointers (SP, BP), and the FLAGS register.
These are the architectural Registers in CPU of the processor. AX, BX, CX, DX, SI, and DI are usually considered general purpose, although some have additional special purposes.
SI and DI, for example, are used with the string instructions, CX is used for hardware looping, some addressing modes use BX, and so on.
Other registers, such as FLAGS and IP, have very specific special purposes and cannot be used for general arithmetic.
If you open up an 8086 built in 1979, you can find the transistors that implement each of these architectural registers, along with some additional microarchitectural registers for the Bus Interface Unit (BIU) and Execution Unit (EU).
The processor itself is fairly simple, and nearly everything in the programmer’s model is readily identifiable in the silicon.
But, if you instead open up a modern 8086-compatible processor, you won’t be able to do the same. Rather, the processor likely has a very large, very complex pipeline.
It has one or more rename register files, which allows it to associate multiple physical registers with a single architectural register.
All of those are microarchitectural registers.
That’s separate from the many, many architectural registers added to the x86 programmer’s model over the years, such as the floating point registers, MMX registers, XMM, YMM, and so on.
I’ve used x86 as an example. But, it’s not unique in this regards. For example, if you look at the ARM v1 processor, you can clearly see each of its architectural registers in silicon.
You can even see that the PC is only 24 bits, missing the upper 6 and lower 2, while the rest are 32 bits.
But, if you were to open up a relatively modern ARM Cortex-A15, you’d find there’s a 128-entry register rename file, and lots of out-of-order behavior in there.
It’s a very different microarchitecture from its 30 year older cousin.
Registers in CPU – How to Know ?
So how many registers are there in a CPU? It really depends on the processor architecture, and its specific implementation!
I’ve also left out the stranger birds, such as the TMS9900 processor.
It has only 3 architectural registers on chip (program counter, status word, and the workspace pointer).
The assembly code, however, refers to registers R0 through R15.
You can actually change the value of the workspace pointer to get multiple “register” sets.
Also, many microcontrollers, such as the MCS-51 family, blur the line between register and on-chip RAM, by carving both out of a common set of on-chip storage.
The general purpose registers, special function registers (SFRs) and on-chip RAM are all mixed together in one address space. (The ACC and B registers are separate though.)
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